The present invention relates generally to semiconductor memory devices and more particularly to a method for manufacturing a capacitor in a semiconductor memory device.
Semiconductor devices including both memory and logic products are developed with what is known as large scale integration (LSI) in which millions of devices can be integrated on a single chip. In these cases, much effort has been put forth in developing manufacturing technology in order to build these semiconductor devices. In particular, efforts have been made at developing technology that will enable denser semiconductor memory devices to be manufactured.
Semiconductor memories having a random access can be divided into DRAM (dynamic random access memory) and SRAM (static random access memory). These semiconductor memories are typically developed using MOS (metal oxide semiconductor) transistors, due to their superior integration capabilities and/or lower power consumption. A DRAM typically has a smaller cell size than an SRAM, which allows a DRAM to have a denser memory size and can typically store more bits on a single chip. This allows a lower cost per bit and makes DRAM the preferred semiconductor memory in many applications.
In a DRAM, a memory cell (DRAM cell) has a memory cell transistor (pass transistor) and a capacitor (storage capacitor). The capacitor is connected to the memory cell transistor and is used for storing information. The data value of information stored in a DRAM cell is determined by the presence or absence of charge on the capacitor. Capacitors having a MIM (metal-insulator-metal) structure are widely adopted.
The cost per unit of DRAM can be lowered by increasing the number of DRAM chips that can be manufactured on a single wafer and/or by increasing the amount of data that can be stored on a single DRAM chip. In order to increase the volume of information that can be stored on a single DRAM and/or decrease the cost per bit in a DRAM by decreasing chip size, smaller memory cells are desired. However, as memory cell size decreases, the area of the cell capacitor also decreases. The decrease in capacitor size typically decreases the capacitance. Thus, the capacitor can store less charge. This affects the integrity of the data stored in a DRAM cell. External noise and/or other affects can introduce errors (known as soft errors) in the stored information due to the critical charge required to properly determine a logic value in a DRAM cell.
In order to increase the capacitance of the cell capacitor in a DRAM, high dielectric insulation films have been used as the dielectric for cell capacitors. High dielectric insulation films are typically various forms of oxide films such metal oxides such as tantalum oxide (Ta2O5), lead zirconium titanate (PZT), barium titanate (BTO), and strontium titanate (STO). For example, silicon oxide/dioxide (SiO2) has been used as the dielectric for cell capacitors for many years. Tantalum oxide has a dielectric constant that is approximately ten times higher than the dielectric constant of silicon dioxide. Furthermore, the dielectric constant of tantalum oxide is about four times higher than that of silicon nitride, which has been used to increase the capacitance of the DRAM cell capacitors.
The capacitance of the cell capacitors can also be increased by increasing the area of the upper and/or lower capacitor electrodes. This can be done by utilizing three-dimensional structures such as cylindrical, boxy, or fin type shapes. The capacitance can be increased even further by combining such a three-dimensional structure with a high dielectric constant insulation film.
A conventional method of making a semiconductor memory (DRAM) cell will now be explained with reference to FIGS. 12A to 14F. FIGS. 12A to 14F illustrate cross-sections of a conventional DRAM cell after various process steps have been completed.
Referring now to FIG. 12A, a P-type silicon substrate 51 has pass transistors 60 formed in a memory array region. A separation insulation film 52 such as silicon oxide formed on the substrate base 51 by LOCOS (local oxidation of silicon) method. Inside each active region surrounded by the separation insulation film 52, a gate oxide film 53 and a gate electrode (word line) 54 are formed. A plurality of N-type diffusion regions 55 forming a source region or drain region for transistors 60 are selectively formed. The surface of the device is then covered by an interlayer insulation film 56.
In this manner, an array of MOS-type memory cell transistors 60 are formed. Each include a gate (control) electrode 54 and a plurality of N-type diffusion regions 55 forming source/drain regions.
A contact hole 57 is then formed in the interlayer insulation film 56, so as to allow a later formed capacitor to make an electrical contact with N-type diffusion region 55. A capacitor contact 58, comprising polycrystalline silicon, is then formed in the contact hole 57. A silicon oxide nitride film 61 and plasma oxide film 62 is then formed on the interlayer insulation film 56 and a cylindrical groove 63 is formed through the plasma nitride-oxide film 61 and the plasma silicon oxide film 62 so as to expose the capacitor contact 58.
Referring now to FIG. 12B, a barrier film 65 comprised of a laminated film of TiN/Ti (titanium nitride/titanium) is then formed over the entire surface by means of CVD (chemical vapor deposition). Then, by sputtering only or sputtering in combination with CVD, a lower electrode film 66A is formed over the entire surface. Lower electrode film 66A is fabricated into a lower electrode of a predetermined pattern by patterning in a later process.
Referring now to FIG. 13C, a deposition process is performed so as to embed a resist material 67 inside each cylindrical groove 63.
Referring now to FIG. 13D, the surface of interlayer insulation film 62 is then planarized by etching to remove unneeded regions of barrier film 65 and lower electrode 66.
Referring now to FIG. 14E, resist material 67 inside cylindrical groove 63 is removed by ashing using an oxygen (O2) plasma.
Referring now to FIG. 14F, a capacitance insulation film 68 and an upper electrode film 69A comprising Ta2O5 are then formed over the entire surface with CVD. Then, an upper electrode (not shown) is formed by patterning the upper electrode film 69A into a desired pattern. This completes the manufacturing of memory cell capacitors of a semiconductor memory.
However, the semiconductor memory produced by the afore-mentioned conventional process can have a drawback of inferior leakage current in the capacitor. This can be caused by the ashing of resist film 67 during the step of applying an oxygen plasma (FIG. 14E) after the planarizing step (FIG. 13D). This can cause the surface of lower electrode 66 to be degraded by damage introduced by the oxidizing plasma. Because capacitor insulation film 68 is formed on the degraded surface of lower electrode 66, the quality of capacitor insulation film 68 can also be degraded by the influence of the damaged lower electrode 66. These effects can cause the capacitor leakage current to increase. Such an increase in capacitor leakage current can cause charge to leak from the storage capacitor and can reduce read margins. This can destroy the integrity of data stored on the semiconductor memory, in particularly under xe2x80x9cpausexe2x80x9d conditions.
A method of manufacturing a semiconductor memory device to prevent such effects of degradation of the lower electrode produced during ashing has been disclosed in a Japanese Unexamined Patent Application, First Publication, No. Hei 7-94600 (JP 7-94600). This process will now be explained with reference to FIGS. 15A to 18H. FIGS. 15A to 18H illustrate cross-sections of a conventional DRAM cell after various process steps have been completed.
Referring now to FIG. 15A, a silicon substrate 131 has memory cell transistors 130 formed in a memory array region. Memory cell transistors 130 are formed inside an active region surrounded by channel stopper regions 135 and separation insulation films 133. Each memory cell transistor 130 is comprised of a gate oxidation film 121, gate electrode 123, and source/drain region 125. Source/drain region 125 has a low doping region 125a and a high doping region 125b. An insulation film 127 is formed over gate electrodes 123.
Referring now to FIG. 15B, a contact hole 141a is then formed in interlayer insulation film to expose a source/drain region 125. Contact hole 141a is formed by anisotropic etching of interlayer insulation film 141. Then a doped polysilicon film 143 is formed over the entire surface using a CVD process.
Referring now to FIG. 16C, doped polysilicon film 143 is then etched back to form a plug layer 143a. Then, a barrier layer 113 is formed over the entire surface by sputtering. A lower electrode film 101A is then formed over the entire surface by a CVD method.
Referring now to FIG. 16D, using a PVD (physical vapor deposition) method such as sputtering, a capacitor insulation film 103 comprised of PZT, for example, is then formed over the entire surface.
Referring now to FIG. 17E, a resist pattern 153 is then formed on top of capacitor insulation film 103. Then, using resist pattern 153 as a mask, patterning is carried out by successively anisotropic etching of capacitor insulation film 103, lower electrode film 101A and barrier film 113. This process forms lower electrode 101 of a desired pattern. Resist pattern 153 is then removed by ashing.
Referring now to FIG. 17F, after resist pattern 153 is removed by ashing, an insulation film 111 comprising a silicon oxide or silicon nitride film is formed over the entire surface using a CVD process.
Referring now to FIG. 18G, insulation film 111 is etched back using anistotropic etching until capacitor insulation film 103 is exposed. A sidewall insulation film 111a is then formed to cover the sidewall surfaces of lower electrode 101 and capacitor insulation film 103.
Referring now to FIG. 18H, an upper electrode 105 is formed over the entire surface to form capacitor 110. Capacitor 110 is comprised of lower electrode 101, capacitor insulation film 103, and upper electrode 105. Then an insulation film 145 is formed over the entire surface, thus completing the conventional manufacturing of memory cells of a semiconductor memory.
According to the conventional manufacturing method disclosed in JP 7-94600, as in the steps illustrated in FIG. 16D and 17E, after forming lower electrode film 101A and capacitor insulation film 103 in succession, lower electrode film 101A and capacitor insulation film 103 are patterned using resist pattern 153 as a mask. Then, resist pattern 153 is removed by ashing. Therefore, when ashing resist pattern 153, lower electrode film 101A is not exposed to the oxygen plasma so that the surface of lower electrode film 101A is not damaged. Thus, capacitor insulation film 103 is not deteriorated and capacitor leakage current may not be increased.
However, in the conventional manufacturing method disclosed in JP 7-94600, although deterioration in the upper electrode film may be prevented during ashing of the resist masking, the capacitor insulation film 103 can be damaged during the process of forming sidewall insulation film 111a. 
According to the semiconductor memory manufacturing method described above, in the step indicated in FIG. 17F, during the step of forming insulation film 111 using a CVD method, damage can be created on capacitor insulation film 103, which has already been formed. In particular, when capacitor insulation film 103 is made of a combination of an oxide film such as Ta2O5 and insulation film 111 is made of a silicon oxide or silicon nitride film, the silicon oxide or silicon nitride film is produced by a reduction reaction of silane such as mono-silane (SiH4) as the raw material. Ta2O5 film can be reduced during this film forming step.
Next, in the step shown in FIG. 18G, capacitor film 103 can be further damaged during the process of forming wall insulation film 111a by anisotropic etching in order to etch back the insulation film 111 formed by the process described above. Accordingly, because capacitor insulation film 103 can be damaged during the step of forming insulation film 111 or during an etch back step, capacitor insulation film 103 can be degraded. This can result in increasing the leakage current of the capacitor in the memory cell.
Furthermore, according to the semiconductor memory manufacturing method disclosed in JP 7-94600, when forming sidewall insulation film 111a as shown in FIG. 18G, fabrication precision during the anisotropic etching is important, but the control of anisotropic etching is difficult and over-etching can occur.
Referring now to FIG. 19, a cross-sections of a conventional DRAM cell when over-etching sidewall insulation film 111a is severe is set forth. It can be seen that if the degree of over-etching is severe, the film thickness of wall insulation film 111a can be reduced and lead to a situation of shorting lower electrode 101 and upper electrode 105.
In view of the above discussion, it would be desirable to provide a method for manufacturing a semiconductor memory and a capacitor that reduces damage to the capacitor insulation film. It would also be desirable to prevent increased leakage current in the memory cell capacitor.
According to the present embodiments, a method of manufacturing a semiconductor capacitor is provided. The capacitor can be formed in a groove formed in an interlayer insulation film. The capacitor can have a lower electrode including a selective growth film, which may be selectively deposited on a lower electrode film.
According to one aspect of the embodiments, groove may be a cylindrical groove.
According to another aspect of the embodiments, an interlayer insulation film may be formed over a semiconductor substrate. A capacitor contact hole may be formed in the interlayer insulation film and a capacitor contact may be formed in the capacitor contact hole.
According to another aspect of the embodiments, the capacitor contact may provide an electrical connection between a diffusion region a lower electrode of a capacitor.
According to another aspect of the embodiments, a lower electrode film may be formed on a surface of the semiconductor including in a groove formed in an interlayer insulation film.
According to another aspect of the embodiments, a resist material may be applied and processed to leave a resist film in a groove formed in an interlayer insulation film.
According to another aspect of the embodiments, excess portions of a lower electrode may be removed so as to leave the lower electrode film in a groove formed in an interlayer insulation layer.
According to another aspect of the embodiments, a resist film in a groove formed in the interlayer insulation film may be removed by ashing using an oxygen plasma.
According to another aspect of the embodiments, a selective growth film may be deposited on an upper electrode formed in a groove formed in an interlayer insulation film.
According to another aspect of the embodiments, the selective growth film may include ruthenium having a thickness of approximately 5xcx9c10 nm.
According to another aspect of the embodiments, the selective growth film may be formed by means of chemical vapor deposition or physical vapor deposition or a combination of chemical vapor deposition and physical vapor deposition.
According to another aspect of the embodiments, a capacitor insulation film may be formed over the selective growth film in the groove formed in an interlayer insulation layer.
According to another aspect of the embodiments, the capacitor film may include one of the group of tantalum oxide, lead zirconium titanate, barium titanate, or strontium titanate.
According to another aspect of the embodiments, an upper electrode film may be formed over a capacitor insulation film.
According to another aspect of the embodiments, the upper electrode film may include a ruthenium film having a thickness of approximately 5xcx9c20 nm.
According to another aspect of the embodiments, an upper capacitor electrode can include a tungsten film.
According to another aspect of the embodiments, the capacitor may be included in a semiconductor memory cell including a memory cell transistor, and the capacitor contact may provide an electrical connection between the lower electrode of the capacitor and a diffusion region of the memory cell transistor.
According to another aspect of the embodiments, the capacitor may be included in a DRAM cell.
According to another aspect of the embodiments, an interlayer insulation film may be formed on the semiconductor substrate and a bit contact hole may be formed in a selected region of the interlayer insulation film providing an opening to a diffusion region associated with at least one memory cell transistor.
According to another aspect of the embodiments, a barrier film may be formed in a bit contact hole.
According to another aspect of the embodiments, a plug may be formed in the bit contact hole, the plug can include a tungsten film.
According to another aspect of the embodiments, bit lines may be formed providing an electrical connection between a column of memory cells. The bit line may include a TiN film having a thickness of approximately 30xcx9c50 nm.